Real space transfer (RST) semiconductor devices are known in the art. See, for instance, S. Luryi's chapter in "Heterojunction Band Discontinuities: Physics and Device Applications", F. Capasso et al., editors, Elsevier 1987, especially pages 513-539, incorporated herein by reference.
Recently, "top-collector" RST devices were disclosed. See M. R. Hueschen et al., Applied Physics Letters, Vol. 57(4), p. 386; and K. Maezawa et al., Japanese Journal of Applied Physics, Vol. 30(6), p. 1190. In these devices the lateral extent of the collector is defined by lithography, and can consequently be small. Thus, the parasitic capacitance that is typically associated with conventional RST devices can be substantially reduced. However, the prior art top-collector devices present another problem. As those spilled in the art will appreciate, both source and drain contacts must be self-aligned with the collector, in order to avoid introduction of (speed-degrading) series resistance into the channel. However, alloying of such self-aligned contacts frequently degrades the integrity of the barrier layer, leading to an increase in undesirable parasitic leakage across the barrier.
In view of the many advantageous features of RST devices, including potentially high speed, it would be highly desirable to have available device geometries that can result in devices that are free of, or at least less subject to, some of the shortcomings associated with prior art geometries.
The potential speed advantage of an inverted ("collector-up") heterojunction bipolar transistor (HBT) structure over the conventional ("emitter-up") structure has long been recognized. See, for instance, H. Kroemer, Proceedings of the IEEE, Vol. 70(1), pp. 13-25 (1982); and C. G. Fonstad, IEEE Electron Device Letters, Vol. EDL-5(3), pp. 99-100 (1984). The advantage of the inverted structure results mainly from a reduction in the parasitic base-collector capacitance that is associated with the extrinsic base region.
Key to a successful implementation of a collector-up HBT is the reduction of the parasitic injection of minority carriers in the extrinsic base region. Several ways of accomplishing this have been proposed, including formation of a p-n junction in the wide-gap emitter layer by ion implantation (see H. Kroemer, op. cit.), and the formation of a buried isolation layer by O.sup.+ implantation. See, for instance, H. Sato et al., IEEE Electron Device Letters, Vol. 11 (10), pp. 457-459 (1990). However, prior art approaches to the manufacture have not proven entirely successful. For instance, it has been found that by ion implantation techniques it is difficult to reliably eliminate the unwelcome injection of minority carriers into extrinsic regions of the base, not covered by the collector stripe. Thus, in view of the advantages that are potentially associated with HBTs of novel geometry, a method of making such devices that is not subject to the shortcomings of prior art techniques would be highly desirable. This application discloses such a method.